HD6475328CG Datasheet, PDF (453/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

ZTAT Versions
P10 / ø*
RES
Internal reset signal
T1
T2
T3
T1
A7 to A0
P63 /A19 to P60 to A16 and
P57 /A15 to P50/A8
R/W
AS, RD and DS (read)
H’00
High impedance
WR and DS (write)
D7 to D0 (write)
High impedance
I/O ports
High impedance
* _{The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,}
but a clock output pin if the DDR bit is 1.
Figure E-7 Reset during Memory Access (Mode 4)
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