HD6475328CG Datasheet, PDF (73/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table 3-11 Arithmetic Instructions (cont)
Instruction
Arithmetic
operations
EXTS
Size
B
EXTU B
TST B/W
NEG B/W
CLR B/W
TAS B
Note: B—byte; W—word
Function
(<bit 7> of <Rd>) → (<bits 15 to 8> of <Rd>)
Converts byte data in a general register to word data by
extending the sign bit.
0 → (<bits 15 to 8> of <Rd>)
Converts byte data in a general register to word data by
padding with zero bits.
(EAd) – 0
Compares general register or memory contents with 0.
0 – (EAd) → (EAd)
Obtains the two’s complement of general register or
memory contents.
0 → (EAd)
Clears general register or memory contents to 0.
(EAd) — 0, (1)2 → (<bit 7> of <EAd>)
Tests general register or memory contents, then sets the
most significant bit (bit 7) to “1.”
3.5.4 Logic Operations
Table 3-12 lists the four instructions that perform logic operations.
Table 3-12 Logic Operation Instructions
Instruction
Logical
AND
operations
OR
Size
B/W
B/W
XOR B/W
NOT B/W
Note: B—byte; W—word
Function
Rd∧(EAs) → Rd
Performs a logical AND operation on a general register
and another general register, memory, or immediate data.
Rd∨(EAs) → Rd
Performs a logical OR operation on a general register and
another general register, memory, or immediate data.
Rd⊕(EAs) → Rd
Performs a logical exclusive OR operation on a general register
and another general register, memory, or immediate data.
¬ (EAd) → (EAd)
Obtains the one’s complement of general register or memory
contents.
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