HD6475328CG Datasheet, PDF (373/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table A-7 Instruction Execution Cycles (4)
Addressing mode
Instruction
SHLR.B
SHLR.W
STC.B
STC.W
SUB.B
SUB.W
SUBS.B
SUBS.W
SUBX.B
SUBX.W
SWAP
TAS
TST.B
TST.W
XCH
XOR.B
XOR.W
XORC
DIVXU.B Zero divide, minimum mode
DIVXU.B Zero divide, maximum mode
DIVXU.W Zero divide, minimum mode
DIVXU.W Zero divide, maximum mode
DIVXU.B Overflow
DIVXU.W Overflow
*
For register and immediate
operands
For memory operand
1
K
J
1
1
2
3
11
2
3
2
3
2 1 2 7 7 8 78 7 8
4 1 2 7 7 8 78 7 8
1 1 2 7 7 8 78 7 8
2 1 2 7 7 8 78 7 8
1 1 2 5 5 6 56 5 6 3
2 1 2 5 5 6 56 5 6
4
1 1 3 5 5 6 56 5 6 3
2 1 3 5 5 6 56 5 6
4
1 1 2 5 5 6 56 5 6 3
2 1 2 5 5 6 56 5 6
4
13
2 1 4 7 7 8 78 7 8
1 1 2 5 5 6 56 5 6
2 1 2 5 5 6 56 5 6
14
1 1 2 5 5 6 56 5 6 3
4 1 4 5 5 6 56 5 6
4
1
59
*
6
7
1
10
11
1
6
8
1
10
12
1
11
21
20 23 23 24 23 24 23 24 21
25 28 28 29 28 29 28 29 21
20 23 23 24 23 24 23 24
27
25 28 28 29 28 29 28 29
27
8 11 11 12 11 12 11 12 9
8 11 11 12 11 12 11 12
10
364