MC9S12NE64CPVE Datasheet, PDF (93/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Functional Description
Read: Register FCLKDIV
Clock Register
Loaded
Check
Bit FDIVLD set? ^no
yes
Write: Register FCLKDIV
Write: Flash address to start
1. ^{compression and number of}
word addresses to compress (max 16,384)
2.
Write: Register FCMD
Data Compress Command 0x06
3.
Write: Register FSTAT
Clear bit CBEIF 0x80
NOTE: command write sequence
aborted by writing 0x00 to
FSTAT register.
NOTE: command write sequence
aborted by writing 0x00 to
FSTAT register.
Read: Register FSTAT
Access
Error Check
Bit
ACCERR
yes
Set?
no
Write: Register FSTAT
Clear bit ACCERR 0x10
Bit Polling for
Command
Completion Check
Bit
CCIF
no
Set?
yes
Read: Register FDATA
Data Compress Signature
Read: Register FSTAT
Signature
Compared to
Known Value
Signature
no
Valid?
yes
Erase and Reprogram
Flash Region Compressed
EXIT
Figure 2-23. Example Data Compress Command Flow
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
93