MC9S12NE64CPVE Datasheet, PDF (262/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 9 Serial Peripheral Interface (SPIV3)
9.1.3 Block Diagram
Figure 9-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data
registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
SPI
SPI
Interrupt
Request
Bus Clock
2
SPI Control Register 1
2
SPI Control Register 2
BIDIROE
SPC0
SPI Status Register
SPIF MODF SPTEF
Interrupt Control
Baud Rate Generator
Counter
Slave
Control
CPOL
CPHA
Phase + SCK in
Slave Baud Rate ^Polarity
Control
Master Baud Rate
Phase + SCK out
Polarity
Control
Port
Control
Master
Logic
Control
Prescaler Clock Select ^{Baud Rate}
Shift
Clock
Sample
Clock
SPPR 3 SPR 3
SPI Baud Rate Register
Shifter
LSBFE=1
LSBFE=0
data in
SPI Data Register
8
LSBFE=1
8
MSB
LSB
LSBFE=0
LSBFE=0
LSBFE=1
data out
MOSI
SCK
SS
Figure 9-1. SPI Block Diagram
9.2 External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPIV3 module has a total of four external pins.
9.2.1 MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
MC9S12NE64 Data Sheet, Rev. 1.1
262
Freescale Semiconductor