MC9S12NE64CPVE Datasheet, PDF (22/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 1 MC9S12NE64 Device Overview
1.1.3 Block Diagram
TEST
64K Byte FLASH EEPROM
8K Byte RAM
VDDX1,2
VDDR /
VREGEN
VDD1,2
VSS1,2
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
Voltage Regulator
Single-wire Background
Debug Module
Debugger
Breakpoints
Clock and Reset
Generator
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
NOACC
XADDR14
Expanded Bus
Interface
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
XCS
ECS/ROMCTL
Multiplexed Address/Data Bus
DDRA
PTA
DDRB
PTB
VRH
VRL
VDDA
VSSA
Analog-to-Digital
Converter
Timer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
IOC4
IOC5
IOC6
IOC7
Serial Communication
Interface 0
Serial Communication
Interface 1
Serial Peripheral
Interface
RXD
TXD
RXD
TXD
MISO
MOSI
SCK
SS
IIC
SDA
SCL
MII_MDC
MII_MDIO
MII_CRS
MII_COL
KWJ6
KWJ7
KWJ0
KWJ1
KWJ2
KWJ3
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXCLK
MII_RXDV
MII_RXER
EMAC
KWG0
KWG1
KWG2
KWG3
KWG4
KWG5
KWG6
KWG7
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_TXCLK
MII_TXEN
MII_TXER
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
VRH
VRL
VDDA
VSSA
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PJ6
PJ7
PJ0
PJ1
PJ2
PJ3
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
Multiplexed
Wide Bus
10BASE-T/
100BASE-TX
Ethernet
Physical
Transceiver
ACTLED
LNKLED
SPDLED
DUPLED
COLLED
PHY_RBIAS
Multiplexed
Narrow Bus
PHY_TXP
PHY_TXN
PHY_RXP
PHY_RXN
Signals shown in Bold are not available on the 80-pin package
(EPHY)
Figure 1-1. MC9S12NE64 Block Diagram
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PHY_VSSA
PHY_VDDA
PHY_VSSRX
PHY_VDDRX
PHY_VSSTX
PHY_VDDTX
MC9S12NE64 Data Sheet, Rev 1.0
22
Freescale Semiconductor