MC9S12NE64CPVE Datasheet, PDF (55/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Signal Description
1.2.3.46 PL0 / ACTLED — Port L I/O Pin 0
PL0 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the active status signal (ACTLED). While in reset and
immediately out of reset, the PL0 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.47 PS7 / SPI_SS — Port S I/O Pin 7
PS7 is a general-purpose I/O. When the serial peripheral interface (SPI) is enabled, PS7 becomes the slave
select pin SS. While in reset and immediately out of reset, the PS7 pin is configured as a high-impedance
input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SPI block
description chapter for information about pin configurations.
1.2.3.48 PS6 / SPI_SCK — Port S I/O Pin 6
PS6 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS6 becomes the
serial clock pin, SCK. While in reset and immediately out of reset, the PS6 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the SPI block description chapter for information about pin configurations.
1.2.3.49 PS5 / SPI_MOSI — Port S I/O Pin 5
PS5 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS5 becomes the
master output (during master mode) or slave input (during slave mode) pin. While in reset and immediately
out of reset, the PS5 pin is configured as a high-impedance input pin. See the port integration module
(PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about
pin configurations.
1.2.3.50 PS4 / SPI_MISO — Port S I/O Pin 4
PS4 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS4 becomes the
master input (during master mode) or slave output (during slave mode) pin. While in reset and immediately
out of reset, the PS4 pin is configured as a high-impedance input pin. See the port integration module
(PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about
pin configurations.
1.2.3.51 PS3 / SCI1_TXD — Port S I/O Pin 3
PS3 is a general-purpose I/O. When the serial communications interface 1 (SCI1) transmitter is enabled,
PS3 becomes the transmit pin, TXD, of SCI1. While in reset and immediately out of reset, the PS3 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
55