MC9S12NE64CPVE Datasheet, PDF (126/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.4.7 Interrupt Enable Register (PIEH)
Module Base + $1E
Read:
Write:
Reset:
Bit 7
0
—
6
PIEH6
0
5
PIEH5
0
4
PIEH4
0
3
PIEH3
0
2
PIEH2
0
1
PIEH1
0
Bit 0
PIEH0
0
= Reserved or unimplemented
Figure 3-29. Port H Interrupt Enable Register (PIEH)
Read:Anytime.
Write:Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port H.
PIEH[6:0] — Interrupt Enable Port H
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
3.3.2.4.8 Interrupt Flag Register (PIFH)
Module Base + $1F
Read:
Write:
Reset:
Bit 7
0
—
6
PIFH6
0
5
PIFH5
0
4
PIFH4
0
3
PIFH3
0
2
PIFH2
0
1
PIFH1
0
Bit 0
PIFH0
0
= Reserved or unimplemented
Figure 3-30. Port H Interrupt Flag Register (PIFH)
Read:Anytime.
Write:Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSH register. To clear this flag, write a “1” to the corresponding bit in the PIFH register.
Writing a “0” has no effect.
PIFH[6:0] — Interrupt Flags Port H
1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable
bit is set).
Writing a “1” clears the associated flag.
0 = No active edge pending.
Writing a “0” has no effect.
MC9S12NE64 Data Sheet, Rev. 1.1
126
Freescale Semiconductor