MC9S12NE64CPVE Datasheet, PDF (123/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Memory Map and Register Descriptions
PIFG[7:0] — Interrupt Flags Port G
1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable
bit is set).
Writing a “1” clears the associated flag.
0 = No active edge pending.
Writing a “0” has no effect.
3.3.2.4 Port H Registers
3.3.2.4.1 I/O Register (PTH)
Module Base + $18
Read:
Write:
EMAC
KWU
Reset:
Bit 7
0
6
PTH6
5
PTH5
4
PTH4
3
PTH3
2
PTH2
1
PTH1
Bit 0
PTH0
MII_TXER MII_TXEN MII_TXCLK MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
KWH
—
0
0
0
0
0
0
0
= Reserved or unimplemented
Figure 3-23. Port H I/O Register (PTH)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The EMAC MII external interface takes precedence over general-purpose I/O function if the EMAC
module is enabled in external PHY mode. If the EMAC MII external interface is enabled PH[6:0] pins
become MII_TXER, MII_TXEN, MII_TXCLK, MII_TXD[3:0]. Please refer to the EMAC block
description chapter for details.
3.3.2.4.2 Input Register (PTIH)
Module Base + $19
Read:
Write:
Reset:
Bit 7
0
—
6
PTIH6
—
5
PTIH5
—
4
PTIH4
—
3
PTIH3
—
2
PTIH2
—
= Reserved or unimplemented
Figure 3-24. Port H Input Register (PTIH)
Read:Anytime.
Write:Never, writes to this register have no effect.
1
PTIH1
—
Bit 0
PTIH0
—
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
123