MC9S12NE64CPVE Datasheet, PDF (423/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 16
Module Mapping Control (MMCV4)
16.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core
platform.
The block diagram of the MMC is shown in Figure 16-1.
SECURE
BDM_UNSECURE
STOP, WAIT
MMC
SECURITY
MMC_SECURE
READ & WRITE ENABLES
CLOCKS, RESET
MODE INFORMATION
EBI ALTERNATE ADDRESS BUS
EBI ALTERNATE WRITE DATA BUS
EBI ALTERNATE READ DATA BUS
CPU ADDRESS BUS
CPU READ DATA BUS
CPU WRITE DATA BUS
CPU CONTROL
REGISTERS
ADDRESS DECODE
INTERNAL MEMORY
EXPANSION
BUS CONTROL
PORT K INTERFACE
MEMORY SPACE SELECT(S)
PERIPHERAL SELECT
CORE SELECT (S)
ALTERNATE ADDRESS BUS (BDM)
ALTERNATE WRITE DATA BUS (BDM)
ALTERNATE READ DATA BUS (BDM)
Figure 16-1. MMC Block Diagram
The MMC is the sub-module which controls memory map assignment and selection of internal resources
and external space. Internal buses between the core and memories and between the core and peripherals is
controlled in this module. The memory expansion is generated in this module.
16.1.1 Features
• Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM)
memory blocks and associated registers
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
423