MC9S12NE64CPVE Datasheet, PDF (144/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 4 Clocks and Reset Generator (CRGV4)
V_DDPLL
MCU
CS
CP
RS
XFC
Figure 4-2. PLL Loop Filter Connections
4.2.3 RESET — Reset Pin
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRGV4.
4.3.1 Module Memory Map
Table 4-1 gives an overview on all CRGV4 registers.
Table 4-1. CRGV4 Memory Map
Address
Offset
Use
0x0000 CRG Synthesizer Register (SYNR)
0x0001
0x0002
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)¹
0x0003 CRG Flags Register (CRGFLG)
0x0004 CRG Interrupt Enable Register (CRGINT)
0x0005 CRG Clock Select Register (CLKSEL)
0x0006 CRG PLL Control Register (PLLCTL)
0x0007 CRG RTI Control Register (RTICTL)
0x0008
0x0009
0x000A
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)²
CRG Test Control Register (CTCTL)³
0x000B CRG COP Arm/Timer Reset (ARMCOP)
1 _{CTFLG is intended for factory test purposes only.}
2 _{FORBYP is intended for factory test purposes only.}
3 _{CTCTL is intended for factory test purposes only.}
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MC9S12NE64 Data Sheet, Rev. 1.1
144
Freescale Semiconductor