MC9S12NE64CPVE Datasheet, PDF (390/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 14 Interrupt (INTV1)
14.3.2.2 Interrupt Test Registers
R
W
Reset
7
INTE
0
6
INTC
5
INTA
4
INT8
3
INT6
2
INT4
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-3. Interrupt TEST Registers (ITEST)
1
INT2
0
0
INT0
0
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt
sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always
return 0s in normal modes.
Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
Table 14-3. ITEST Field Descriptions
Field
7:0
INT[E:0]
Description
Interrupt TEST Bits — These registers are used in special modes for testing the interrupt logic and priority
independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a
logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0. These bits can be
written only in special modes and only with the WRTINT bit set (logic 1) in the interrupt test control register
(ITCR). In addition, I interrupts must be masked using the I bit in the CCR. In this state, the interrupt input lines
to the interrupt sub-block will be disconnected and interrupt requests will be generated only by this register.
These bits can also be read in special modes to view that an interrupt requested by a system block (such as a
peripheral block) has reached the INT module.
There is a test register implemented for every eight interrupts in the overall system. All of the test registers share
the same address and are individually selected using the value stored in the ADR[3:0] bits of the interrupt test
control register (ITCR).
Note: When ADR[3:0] have the value of 0x000F, only bits 2:0 in the ITEST register will be accessible. That is,
vectors higher than 0xFFF4 cannot be tested using the test registers and bits 7:3 will always read as a
logic 0. If ADR[3:0] point to an unimplemented test register, writes will have no effect and reads will always
return a logic 0 value.
14.3.2.3 Highest Priority I Interrupt (Optional)
7
6
5
4
3
2
1
0
R
0
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
W
Reset
1
1
1
1
0
0
1
0
= Unimplemented or Reserved
Figure 14-4. Highest Priority I Interrupt Register (HPRIO)
Read: Anytime
Write: Only if I mask in CCR = 1
MC9S12NE64 Data Sheet, Rev. 1.1
390
Freescale Semiconductor