MC9S12NE64CPVE Datasheet, PDF (546/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Appendix B Schematic and PCB Layout Design Recommendations
B.2 PCB Design Recommendation
The section provides recommendations for general HCS12 PCB design and recommendations for PCB
design with Ethernet.
B.2.1 General PCB Design Recommendations
The PCB layout must be designed to ensure proper operation of the voltage regulator and the MCU. The
following recommendations are provided to ensure a robust PCB design:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
• Central point of the ground star should be the VSSX pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSX.
• VSSPLL must be directly connected to VSSX.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for
C7,C8, C11 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
B.2.2 Ethernet PCB Design Recommendations
When designing a PCB that uses the MC9S12NE64 Ethernet module, several design considerations must
be made to ensure that Ethernet operation conforms to the IEEE 802.3 physical interface specification.
These Ethernet PCB design recommendations include:
• The distance between the magnetic module and the RJ-45 jack is the most critical and must always
be as short as possible (less than one inch).
• Never use 90° traces. Use 45° angles or radius curves in traces.
• Trace widths of 0.010” are recommended. Wider is better. Trace widths should not vary.
• Route differential Tx and Rx pairs near together (max 0.010” separation with 0.010” traces).
• Trace lengths must always be as short as possible (must be less than one inch).
• Make trace lengths as equal as possible.
• Keep TX and RX differential pairs routes separated (at least 0.020” separation). Better to separate
with a ground plane.
• Avoid routing Tx and Rx traces over or under a plane. Areas under the Tx and Rx traces should be
open.
• Use precision components in the line termination circuitry with 1% tolerance.
• Ensure that the power supply is rated for a load of 300 mA minimum.
• Avoid vias and layer changes.
MC9S12NE64 Data Sheet, Rev. 1.1
546
Freescale Semiconductor