MC9S12NE64CPVE Datasheet, PDF (65/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Block Configuration for MC9S12NE64
1.7.3 Clock Reset Generator (CRG)
See the CRG chapter for information about the clock and reset generator module. For the MC9S12NE64,
only the Pierce circuitry is available for the oscillator.
The low-voltage reset feature uses the low-voltage reset signal from the VREG_PHY module as an input
to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a
specified threshold, the LVR signal from the VREG_PHY module causes the CRG module to generate a
reset. See the VREG_PHY block description chapter for voltage level specifications.
1.7.4 Oscillator (OSC)
See the OSC chapter for information about the oscillator module. The XCLKS input signal is not available
on the MC9S12NE64. The signal is internally tied low to select the Pierce oscillator or external clock
configuration.
1.7.5 Ethernet Media Access Controller (EMAC)
See the EMAC chapter for information about the Ethernet media access controller module. The EMAC is
part of the IPBus domain.
1.7.5.1 EMAC MII External Pin Configuration
When the EMAC is configured for and external Ethernet physical transceiver internal pull-ups and
pull-downs are not automatically configured on the MII inputs. Any internal pull-up or pull-down resistors,
which may be required, must be configured by setting the appropriate pull control registers in the port
integration module (PIM). This implementation allows the use of external pull-up and pull-down resistors.
1.7.5.2 EMAC Internal PHY Configuration
When the EXTPHY bit (in the EMAC NETCTL register) is set to 1, the EMAC is configured to work with
the internal EPHY block. Please see 1.7.6, “Ethernet Physical Transceiver (EPHY),” for more information
regarding the EPHY block.
1.7.5.3 Low-Power Operation
Special care must be taken when executing STOP and WAIT instructions while using the EMAC, or
undesired operation may result.
1.7.5.3.1 Wait
Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL
register because the clocks to the transmit and receive buffers are stopped. It is recommended that the
EMAC ESWAI bit be set if wait mode is entered with the CWAI set.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
65