MC9S12NE64CPVE Datasheet, PDF (429/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Memory Map and Register Definition
16.3.2.3 Initialization of Internal EEPROM Position Register (INITEE)
7
6
5
4
3
2
R
0
EE15
EE14
EE13
EE12
EE11
W
Reset¹
—
—
—
—
—
—
1
0
0
EEON
—
—
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
actual reset state of this register.
= Unimplemented or Reserved
Figure 16-5. Initialization of Internal EEPROM Position Register (INITEE)
Read: Anytime
Write: The EEON bit can be written to any time on all devices. Bits E[11:15] are “write anytime in all
modes” on most devices. On some devices, bits E[11:15] are “write once in normal and emulation modes
and write anytime in special modes”. See device overview chapter to determine the actual write access
rights.
NOTE
Writes to this register take one cycle to go into effect.
This register initializes the position of the internal EEPROM within the on-chip system memory map.
Table 16-4. INITEE Field Descriptions
Field
Description
7:3
EE[15:11]
0
EEON
Internal EEPROM Map Position — These bits determine the upper five bits of the base address for the system’s
internal EEPROM array.
Enable EEPROM — This bit is used to enable the EEPROM memory in the memory map.
0 Disables the EEPROM from the memory map.
1 Enables the EEPROM in the memory map at the address selected by EE[15:11].
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
429