MC9S12NE64CPVE Datasheet, PDF (488/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 18 Debug Module (DBGV1)
18.3.2.10 Debug Comparator A Register (DBGCA)
15
R
Bit 15
W
14
Bit 14
13
Bit 13
12
Bit 12
11
Bit 11
10
Bit 10
9
Bit 9
8
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 18-17. Debug Comparator A Register High (DBGCAH)
R
W
Reset
Field
15:0
15:0
7
Bit 7
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
Figure 18-18. Debug Comparator A Register Low (DBGCAL)
Table 18-21. DBGCA Field Descriptions
Description
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See Table 18-20.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.2.11 Debug Comparator B Extended Register (DBGCBX)
7
6
5
4
3
2
1
0
R
PAGSEL
W
EXTCMP
Reset
0
0
0
0
0
0
0
0
Figure 18-19. Debug Comparator B Extended Register (DBGCBX)
Table 18-22. DBGCBX Field Descriptions
Field
Description
7:6
PAGSEL
5:0
EXTCMP
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
Table 18-11.
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in Table 18-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see Table 18-20.
MC9S12NE64 Data Sheet, Rev. 1.1
488
Freescale Semiconductor