MC9S12NE64CPVE Datasheet, PDF (354/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.3.3 MII Registers
Table 12-2 gives an overview of all registers in the EPHY that are accessible via the MII management
interface. These registers are not part of the MCU memory map.
Table 12-2. MII Registers
Address
0
%00000
1
%00001
2
%00010
3
%00011
4
%00100
5
%00101
6
%00110
7
%00111
8
%01000
9
%01001
10
%01010
11
%01011
12
%01100
13
%01101
14
%01110
15
%01111
16
%10000
17
%10001
18
%10010
Use
Control Register
Status Register
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Interrupt Control Register
Proprietary Status Register
Proprietary Control Register
Access
Read/Write
Read/Write⁴
Read/Write⁴
Read/Write⁴
Read/Write
Read/Write⁴
Read/Write⁴
Read/Write
Read/Write¹
Read/Write¹
Read/Write¹
Read/Write¹
Read/Write¹
Read/Write¹
Read/Write¹
Read/Write¹
Read/Write
Read/Write⁴
Read/Write
1. Always read $00
2. Writable only in special modes (test_mode = 1)
4. Write has no effect.
NOTE
Bit notation for MII registers is: Bit 20.15 refers to MII register address 20
and bit number 15.
12.3.3.1 EPHY Control Register
MII Register Address 0 (%00000)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
W
RESET
LOOP
BACK
DATA
RATE
ANE PDWN ISOL
RAN
DPLX
COL
TEST
0
0
0
0
0
0
0
RESET: 0
0
1
X
0
0
0
1
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-6. Control Register
Read: Anytime
Write: Anytime
MC9S12NE64 Data Sheet, Rev. 1.1
354
Freescale Semiconductor