MC9S12NE64CPVE Datasheet, PDF (502/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Appendix A Electrical Characteristics
• PHY_VDDTX, PHY_VSSTX are power supply pins for EPHY transmitter
• V_DDA, V_DDX1, V_DDX2 as well as V_SSA, V_SSX1, V_SSX2 are connected by anti-parallel
diodes for ESD protection.
In the following context:
NOTE
• V_DD3 is used for either V_DDA, V_DDR, and V_DDX1/V_DDX2
• V_SS3 is used for either V_SSA, V_SSR, and V_SSX1/V_SSX2 unless
otherwise noted
• I_DD3 denotes the sum of the currents flowing into the V_DDA,
V_DDR, and V_DDX1/V_DDX2 pins
• V_DD is used for V_DD1, V_DD2, V_DDPLL, PHY_VDDTX,
PHY_VDDRX, and PHY_VDDA
• V_SS is used for V_SS1, V_SS2, V_SSPL, PHY_VSSTX, PHY_VSSRX,
and PHY_VSSA
• I_DD is used for the sum of the currents flowing into V_DD1, V_DD2
• I_DDPHY is used for the sum of currents flowing into
PHY_VDDTX, PHY_VDDRX, and PHY_VDDA
• V_DDPHY is used for PHY_VDDTX, PHY_VDDRX, and
PHY_VDDA
• V_DDTX is used for twisted pair differential voltage present on the
PHY_TXP and PHY_TXN pins
• I_DDTX is used for twisted pair differential current flowing into the
PHY_TXP or PHY_TXN pins
A.3 Pins
There are four groups of functional pins.
A.3.1 3.3 V I/O Pins
These I/O pins have a nominal level of 3.3 V. This group of pins is comprised of all port I/O pins,
the analog inputs, BKGD pin and the RESET inputs. The internal structure of these pins are
identical, however some of the functionality may be disabled.
A.3.2 Analog Reference, Special Function Analog
This group of pins is comprised of the V_RH, V_RL, PHY_TXN, PHY_TXP, PHY_RXN,
PHY_RXP, and R_BIAS pins.
MC9S12NE64 Data Sheet, Rev. 1.1
502
Freescale Semiconductor