MC9S12NE64CPVE Datasheet, PDF (110/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 3 Port Integration Module (PIM9NE64V1)
Table 3-1. Pin Functions and Priorities (Sheet 4 of 4)
Port Pin Name Pin Function
Description
Port S
PS[7]
PS[6]
PS[5]
PS[4]
PS[3]
PS[2]
PS[1]
PS[0]
Port T PT[7:4]
SPI_SS
GPIO
SPI_SCK
GPIO
SPI_MOSI
GPIO
SPI_MISO
GPIO
SCI1_TXD
GPIO
SCI1_RXD
GPIO
SCI0_TXD
GPIO
SCI0_RXD
GPIO
IOC[7:4]
GPIO
Serial Peripheral Interface slave select output in master
mode, input in slave mode or master mode.
General-purpose I/O
Serial Peripheral Interface serial clock pin
General-purpose I/O
Serial Peripheral Interface master out/slave in pin
General-purpose I/O
Serial Peripheral Interface master in/slave out pin
General-purpose I/O
Serial Communication Interface 1 transmit pin
General-purpose I/O
Serial Communication Interface 1 receive pin
General-purpose I/O
Serial Communication Interface 0 transmit pin
General-purpose I/O
Serial Communication Interface 0 receive pin
General-purpose I/O
Standard Timer1 Channels 7 to 4
General-purpose I/O
Pin Function
after Reset
GPIO
GPIO
3.3 Memory Map and Register Descriptions
This section provides a detailed description of all registers.
3.3.1 Module Memory Map
Table 3-2 shows the memory map of the port integration module.
Table 3-2. PIM Module Memory Map
Address
Offset
$00
$01
$02
$03
$04
$05
Use
Port T I/O Register (PTT)
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
Port T Polarity Select Register (PPST)
Access
R/W
R
R/W
R/W
R/W
R/W
MC9S12NE64 Data Sheet, Rev. 1.1
110
Freescale Semiconductor