MC9S12NE64CPVE Datasheet, PDF (516/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Appendix A Electrical Characteristics
A.12 Reset, Oscillator, and PLL Electrical Characteristics
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.12.1 Startup
Table A-11 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the clock and reset generator (CRG) block description chapter.
Table A-11. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min
1
T POR release level
V_PORR
2
T POR assert level
V_PORA
0.97
3
D Reset input pulse width, minimum input time
PW_RSTL
2
4
D Startup from Reset
n_RST
192
5
D Interrupt pulse width, IRQ edge-sensitive
mode
PW_IRQ
20
6
D Wait recovery startup time
7
P LVR release level
8
P LVR assert level
t_WRS
V_LVRR
V_LVRA
2.25
Typ
Max
2.07
196
14
2.55
Unit
V
V
t_osc
n_osc
ns
t_cyc
V
V
A.12.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.12.1.2 LVR
The release level V_LVRR and the assert level V_LVRA are derived from the V_DD supply. They are also valid
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.12.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V_DD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG flags register has not been set.
MC9S12NE64 Data Sheet, Rev. 1.1
516
Freescale Semiconductor