MC9S12NE64CPVE Datasheet, PDF (368/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
• 10BASE-T
• 100BASE-TX
• Low-power
12.4.1 Power Down/Initialization
Upon reset, the EPHYEN bit, in the Ethernet physical transceiver control register 0 (EPHYCTL0), is
cleared and EPHY is in its lowest power consumption state. All analog circuits are powered down. The
twisted-pair transmitter and receiver pins (PHY_TXP, PHY_TXN, PHY_RXP, and PHY_RXN) are
high-impedance. The MII management interface is not accessible. All MII registers are initialized to their
reset state. The ANDIS, DIS100, and DIS10 bits, in the EPHYCTL0 register, have no effect until the
EPHYEN bit is set.
The EPHYEN bit can be set or cleared by a register write at any time. Prior to enabling the EPHY, setting
EPHYEN to 1, the MII PHY address PHYADD[4:0] must be set in the Ethernet physical transceiver
control register 1 (EPHYCTL1), and the ANDIS, DIS100, DIS10 bits, in the EPHYCTL0 register, must
be configured for the desired start-up operation. Whenever the EPHYEN bit transitions from 0 to 1, MDIO
communications must be delayed until the completion of a start-up delay period (t_Start-up, see
Figure 12-19).
MC9S12NE64 Data Sheet, Rev. 1.1
368
Freescale Semiconductor