MC9S12NE64CPVE Datasheet, PDF (340/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 11 Ethernet Media Access Controller (EMACV1)
The exponent k is assigned a value that is equal to either the number of transmission attempts or the number
10, whichever is less. The coefficient r of the slot time is an integer randomly selected from a range of
integers from 0 to one less than the value of two to the exponent k. Table 11-10 shows the range of backoff
times that may occur on a channel.
Table 11-10. Backoff Times
Collision on
Attempt Number
1
2
3
4
5
6
7
8
9
10-15
16
Range of Random
Numbers
0...1
0...3
0...7
0...15
0...31
0...63
0...127
0...255
0...511
0...1023
N/A
Range of Backoff
Times (10 Mbps)
0...51.2 µs
0...153.6 µs
0...358.4 µs
0...768.0 µs
0...1.59 ms
0...3.23 ms
0...6.50 ms
0...13.06 ms
0...26.16 ms
0...52.38 ms
Discard frame
Range of Backoff
Times (100 Mbps)
0...5.1 µs
0...15.4 µs
0...35.8 µs
0...76.8 µs
0...158.7 µs
0...322.6 µs
0...650.2 µs
0...1.31 ms
0...2.62 ms
0...5.24 ms
Discard frame
The RANDOM field in the EMISC register contains the 10-bit random number generated by the random
generator in the backoff logic. If the SSB bit is set, the transmitter backoff logic forces a single slot backoff
time of 512 bit times instead of following the random backoff algorithm.
11.4.3.3.4 Retry Counter
The EMAC transmitter has a retry counter, RETX, that counts the number of collisions within the collision
window period that occur while attempting to send a single frame. The retry counter increments by 1 after
each collision and resets to 0 when each frame is successfully transmitted. RETX is held at 0 when TXACT
is clear. The EMAC transmitter attempts to retransmit up to 15 times. If a collision occurs when RETX is
15, the excessive collision interrupt flag (ECIF) is set to 1, the entire transmit frame is discarded, and the
retry counters resets to 0. If not masked (ECIE set to 1), the EMAC generates the excessive collision
interrupt. The TXACT bit in TXCTS will be asserted for the entire duration of the retry process. The next
transmission can start as soon as TXACT is clear.
11.4.4 Ethernet Buffers
There are two receive Ethernet buffers and one transmit Ethernet buffer allocated within the system RAM.
The size and starting address for each buffer is configured by the BUFMAP field in the BUFCFG register.
See Section 11.3.2.15, “Ethernet Buffer Configuration (BUFCFG).”
11.4.4.1 Receive Ethernet Buffer
Upon reception, the receive Ethernet buffers store the destination address (DA), the source address (SA),
the type/length field, the data field, and the frame check sequence (FCS). If the receiver has data to put into
a receive buffer and the receive buffers are full, the receive frame is dropped. If the length of the receive
frame is larger than the receive buffer, the corresponding receive buffer overrun flag bit is set to 1, and if
MC9S12NE64 Data Sheet, Rev. 1.1
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