MC9S12NE64CPVE Datasheet, PDF (391/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Functional Description
Table 14-4. HPRIO Field Descriptions
Field
Description
7:1
PSEL[7:1]
Highest Priority I Interrupt Select Bits — The state of these bits determines which I-bit maskable interrupt will
be promoted to highest priority (of the I-bit maskable interrupts). To promote an interrupt, the user writes the least
significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or
a non I-bit masked vector address (value higher than 0x00F2) is written, IRQ (0xFFF2) will be the default highest
priority interrupt.
14.4 Functional Description
The interrupt sub-block processes all exception requests made by the CPU. These exceptions include
interrupt vector requests and reset vector requests. Each of these exception types and their overall priority
level is discussed in the subsections below.
14.4.1 Low-Power Modes
The INT does not contain any user-controlled options for reducing power consumption. The operation of
the INT in low-power modes is discussed in the following subsections.
14.4.1.1 Operation in Run Mode
The INT does not contain any options for reducing power in run mode.
14.4.1.2 Operation in Wait Mode
Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be
used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
14.4.1.3 Operation in Stop Mode
Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be
used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
14.5 Resets
The INT supports three system reset exception request types: normal system reset or power-on-reset
request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request
must be decoded by the system and the proper request made to the core. The INT will then provide the
service routine address for the type of reset requested.
14.6 Interrupts
As shown in the block diagram in Figure 14-1, the INT contains a register block to provide interrupt status
and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate
whether pending interrupts are valid and assess their priority.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
391