MC9S12NE64CPVE Datasheet, PDF (358/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
JABDT —Jabber Detect
After it is set, JABDT is cleared each time register 1 is read via the management interface. JABDT is
also cleared by a PHY reset. For 100BASE-TX operation, this signal will always be cleared.
1 = Indicates that a jabber condition has been detected
0 = Indicates that no jabber condition has been detected
EXCAP — Extended capability
1 = Indicates that the extended register set (registers 2–31) has been implemented in the PHY.
0 = Indicates that the extended register set (registers 2–31) has NOT been implemented in the PHY
12.3.3.3 EPHY Identifier Register 1
Registers $_02 and $_03 provide the PHY identification code.
MII Register Address 2 (%00010)
15 14 13 12 11 10
9
R
W
RESET: 0 0 0
0
01
0
0
8
765
4
3
2
1
0
PHYID
0
001
0
1
1
0
0
= Unimplemented or Reserved
Figure 12-8. EPHY Identifier Register 1
Read: Anytime
Write: Writes have no effect — Read only
PHYID — PHY ID Number
Composed of bits 3:18 of the organization unique identifier (OUI).
12.3.3.4 EPHY Identifier Register 2
Registers $_02 and $_03 provide the PHY identification code.
MII Register Address 3 (%00011)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
PHYID
MODELNUMBER
REVISIONNUMBER
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
= Unimplemented or Reserved
Figure 12-9. EPHY Identifier Register 2
Read: Anytime
Write: Writes have no effect — Read only
PHYID — PHY ID number organization unique identifier. Composed of bits 15:10.
MODELNUMBER — Manufacturers model number. Composed of bits 9:4.
REVISIONNUMBER — Manufacturers revision number. Composed of bits 3:0.
MC9S12NE64 Data Sheet, Rev. 1.1
358
Freescale Semiconductor