MC9S12NE64CPVE Datasheet, PDF (46/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 1 MC9S12NE64 Device Overview
Table 1-4. Signal Properties (Sheet 4 of 4)
orig. order
80 Pin
No.
112 Pin
No.
Pin
Name
Function
1
Pin
Name
Function
2
57
51
71
PHY_TXN
—
74
52
72 PHY_VSSTX
—
60
53
73
PHY_RXP
—
59
54
74
PHY_RXN
—
75
55
75 PHY_VDDRX
—
76
56
76 PHY_VSSRX
—
45
57
81
PL2
SPDLED
77
58
82
VDDR/
VREGEN
—
46
59
83
PL1
LNKLED
47
60
84
PL0
ACTLED
16
61–68 85–92 PAD[7:0]
AN[7:0]
78
69
93
VDDA
—
79
70
94
VRH
—
80
71
95
VRL
—
81
72
96
VSSA
—
19
—
97–100
103–104
PK[5:0]
XADDR
[19:14]
82
73
101
VSS1
—
83
74
102
VDD1
—
18
—
105
PK[6]
XCS
17
—
106
PK[7]
ECS
56
75–78 107–110 PT[7:4]
35
79
111
PJ7
36
80
112
PJ6
TIM_IOC
[7:4]
KWJ7
KWJ6
Pin
Name
Function
3
—
—
—
—
—
—
—
Power
Domain
Internal Pull
Resistor
CTRL
Reset
State
Description
Reset
State
PHY_
VDDTX
NA
PHY_
VDDRX
NA
PHY_
VDDRX
NA
NA
Twisted pair output –
Analog
Output
See Table 1-5
NA
Twisted pair input +
Analog
Input
NA
Twisted pair input –
Analog
Input
See Table 1-5
See Table 1-5
VDDX
PERL/
PPSL
Disabled
Port L I/O pin; EPHY
100 Mbps LED
Input
—
See Table 1-5
—
—
—
—
—
—
—
—
—
—
—
ROMCTL
—
IIC_SCL
IIC_SDA
VDDX
VDDX
VDDA
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PERL/
PPSL
PERL/
PPSL
None
PUCR
PUCR
PUCR
PERT/
PPST
PERJ/
PPSJ
PERJ/
PPSJ
Disabled
Port L I/O pin; EPHY
valid link LED
Input
Port L I/O pin; EPHY
Disabled transmit or receive Input
LED
None
Port AD input pins;
ATD inputs
Input
See Table 1-5
See Table 1-5
See Table 1-5
See Table 1-5
Port K I/O pins;
Up extended
addresses
Input
See Table 1-5
See Table 1-5
Up
Port K I/O pin;
external chip select
Input
Port K I/O pin;
Up emulation chip
select;
Input
Port T I/O pins; timer
Disabled TIM input cap.
Input
output compare
Disabled
Port J I/O pin; IIC
SCL; interrupt
Input
Disabled
Port J I/O pin; IIC
SDA; interrupt
Input
MC9S12NE64 Data Sheet, Rev 1.0
46
Freescale Semiconductor