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MC9S12NE64CPVE Datasheet, PDF (167/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview | |||
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Functional Description
Table 4-11. Outcome of Clock Loss in Wait Mode
CME
0
1
1
SCME
X
0
1
SCMIE
CRG Actions
X Clock failure -->
No action, clock loss not detected.
X Clock failure -->
CRG performs Clock Monitor Reset immediately
0 Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting Wait Mode.
â MCU remains in Wait Mode,
â VREG enabled,
â PLL enabled,
â SCM activated,
â Start Clock Quality Check,
â Set SCMIF interrupt ï¬ag.
Some time later OSCCLK recovers.
â CM no longer indicates a failure,
â 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
â SCM deactivated,
â PLL disabled depending on PLLWAI,
â VREG remains enabled (never gets disabled in Wait Mode).
â MCU remains in Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
â Exit Wait Mode using OSCCLK as system clock (SYSCLK),
â Continue normal operation.
or an External Reset is applied.
â Exit Wait Mode using OSCCLK as system clock,
â Start reset sequence.
Scenario 2: OSCCLK does not recover prior to exiting Wait Mode.
â MCU remains in Wait Mode,
â VREG enabled,
â PLL enabled,
â SCM activated,
â Start Clock Quality Check,
â Set SCMIF interrupt ï¬ag,
â Keep performing Clock Quality Checks (could continue inï¬nitely)
while in Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
â Exit Wait Mode in SCM using PLL clock (fSCM) as system clock,
â Continue to perform additional Clock Quality Checks until OSCCLK
is o.k. again.
or an External RESET is applied.
â Exit Wait Mode in SCM using PLL clock (fSCM) as system clock,
â Start reset sequence,
â Continue to perform additional Clock Quality Checks until OSCCLK
is o.k.again.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
167
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