MC9S12NE64CPVE Datasheet, PDF (517/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Reset, Oscillator, and PLL Electrical Characteristics
A.12.1.4 External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.12.1.5 Stop Recovery
Out of stop, the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
A.12.1.6 Pseudo Stop and Wait Recovery
The recovery from pseudo stop and wait are essentially the same because the oscillator was not stopped in
either mode. The controller can be woken up by internal or external interrupts. After t_wrs the CPU starts
fetching the interrupt vector.
A.12.2 Oscillator
The device features an internal Pierce oscillator. Before asserting the oscillator to the internal system
clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail.
t_CQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP
if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up
time t_UPOSC. The device also features a clock monitor. A clock monitor failure is asserted if the frequency
of the incoming clock signal is below the assert frequency f_CMFA.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
517