MC9S12NE64CPVE Datasheet, PDF (241/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

8.3.2.6 SCI Data Registers (SCIDRH and SCIDRL)
Memory Map and Register Definition
7
6
5
4
3
2
1
0
R
R8
0
0
0
0
0
0
T8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9. SCI Data Register High (SCIDRH)
Field
7
R8
6
T8
Table 8-9. SCIDRH Field Descriptions
Description
Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
7
6
5
4
3
2
1
R
R7
R6
R5
R4
R3
R2
R1
W
T7
T6
T5
T4
T3
T2
T1
Reset
0
0
0
0
0
0
0
Figure 8-10. SCI Data Register Low (SCIDRL)
Read: anytime; reading accesses SCI receive data register
Write: anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Field
7:0
R[7:0]
T[7:0}
Table 8-10. SCIDRL Field Descriptions
Description
Received bits 7 through 0 — For 9-bit or 8-bit data formats
Transmit bits 7 through 0 — For 9-bit or 8-bit formats
NOTE
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to SCI data register high (SCIDRH) then to SCIDRL.
Freescale Semiconductor
MC9S12NE64 Data Sheet, Rev. 1.1
0
R0
T0
0
241