MC9S12NE64CPVE Datasheet, PDF (66/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 1 MC9S12NE64 Device Overview
1.7.5.3.2 Stop
During system low-power stop mode, the EMAC is immediately disabled. Any receive in progress is
dropped and any PAUSE time-out is cleared. The user must not to enter low-power stop mode when
TXACT or BUSY are set.
1.7.6 Ethernet Physical Transceiver (EPHY)
See the EPHY chapter for information about the Ethernet physical transceiver module. The EPHY also has
MII register space which is not part of the MCU address space and not accessible via the IP bus. The MII
registers can be accessed using the MDIO functions of the EMAC when the EMAC is configured for
internal PHY operation. The MII pins of the EPHY are not externally accessible. All communication and
management of the EPHY must be performed using the EMAC.
The organization unique identifier (OUI) for the MC9S12NE64 is 00-60-11 (hex).
1.7.6.1 Low-Power Operation
Special care must be taken when executing STOP and WAIT instructions while using the EPHY or
undesired operation may result.
1.7.6.1.1 Wait
Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL
register because the clocks to the internal MII interface are stopped.
1.7.6.1.2 Stop
During system low-power stop mode, the EPHY is immediately reset and powered down. Upon exiting
stop mode, the a start-up delay is required prior to initiating MDIO communications with the EPHY. See
A.14, “EPHY Electrical Characteristics” for details. It is not possible to use an EPHY interrupt to wake
the system from stop mode.
1.7.7 RAM 8K Block Description
This module supports single-cycle misaligned word accesses without wait states.
In addition to operating as the CPU storage, the 8K system RAM also functions as the Ethernet buffer
while the EMAC module is enabled. While the EMAC is enabled, the Ethernet buffer will occupy 0.375K
to 4.5K of RAM with physical addresses starting at $0000 and ending at $017F up to $11FF, depending
on the setting of the BUFMAP bits in the EMAC Ethernet buffer configuration register (BUFCFG). The
relative RAM address, which are controlled by settings in the internal RAM position register (INTRM),
must be tracked in software.
The Ethernet buffer operation of the RAM is independent of the CPU and allows same cycle read/write
access from the CPU and the EMAC. No hardware blocking mechanism is implemented to prevent the
CPU from accessing the Ethernet RAM space, so care must be taken to ensure that the CPU does not
corrupt the RAM Ethernet contents.
MC9S12NE64 Data Sheet, Rev 1.0
66
Freescale Semiconductor