MC9S12NE64CPVE Datasheet, PDF (173/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Resets
Definition.” All reset sources are listed in Table 4-13. Refer to the device overview chapter for related
vector addresses and priorities.
Table 4-13. Reset Summary
Reset Source
Local Enable
Power-on Reset
None
Low Voltage Reset
None
External Reset
None
Clock Monitor Reset PLLCTL (CME=1, SCME=0)
COP Watchdog Reset COPCTL (CR[2:0] nonzero)
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (external reset).
• Power on is detected.
• Low voltage is detected.
• COP watchdog times out.
• Clock monitor failure is detected and self-clock mode was disabled (SCME = 0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see Figure 4-25). Because entry into reset is asynchronous it does not require a running SYSCLK.
However, the internal reset circuit of the CRGV4 cannot sequence out of current reset condition without a
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the
RESET pin is released. The reset generator of the CRGV4 waits for additional 64 SYSCLK cycles and
then samples the RESET pin to determine the originating source. Table 4-14 shows which vector will be
fetched.
Table 4-14. Reset Vector Selection
Sampled RESET Pin
(64 Cycles After
Release)
1
1
1
0
Clock Monitor
Reset Pending
0
1
0
X
COP Reset
Pending
Vector Fetch
0
POR / LVR / External Reset
X
Clock Monitor Reset
1
COP Reset
X
POR / LVR / External Reset
with rise of RESET pin
NOTE
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
173