MC9S12NE64CPVE Datasheet, PDF (381/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

13.2 Signal Description
Signal Description
13.2.1 Overview
Due to the nature of VREG_PHY being a voltage regulator providing the chip internal power
supply voltages most signals are power supply signals connected to pads.
Table 13-1 shows all signals of VREG_PHY associated with pins.
Table 13-1. VREG_PHY - Signal Properties
Name
VDDR
VDDRAUX1
VDDRAUX2
VDDRAUX3
VDDA
VSSA
VDD
VSS
VDDPLL
VSSPLL
VDDAUX1
VSSAUX1
VDDAUX2
VSSAUX2
VDDAUX3
VSSAUX3
VREGEN (optional)
Port
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function
VREG_PHY power input (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY quiet input (positive supply)
VREG_PHY quiet input (ground)
VREG_PHY primary output (positive supply)
VREG_PHY primary output (ground)
VREG_PHY secondary output (positive supply)
VREG_PHY secondary output (ground)
VREG_PHY third output (positive supply)
VREG_PHY third output (ground)
VREG_PHY fourth output (positive supply)
VREG_PHY fourth output (ground)
VREG_PHY fifth output (positive supply)
VREG_PHY fifth output (ground)
VREG_PHY (Optional) Regulator Enable
Reset State
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pull up
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13.2.2 Detailed Signal Descriptions
Check device level specification for connectivity of the signals.
13.2.2.1 VDDR,VDDRAUX1,2,3, VSS - Regulator Power Inputs
Signal VDDR/VDDRAUX1,2,3 are the power inputs of VREG_PHY. All currents sourced into
the regulator loads flow through these pins. A chip external decoupling capacitor (100nF...220nF,
X7R ceramic) between VDDR/VDDRAUX1,2,3 and VSS can smoothen ripple on
VDDR/VDDRAUX1,2,3.
If the regulator shall be bypassed, VDDR should be tied to ground. In Shutdown Mode pin VDDR
should also be tied to ground on devices without VREGEN pin.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
381