MC9S12NE64CPVE Datasheet, PDF (117/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Memory Map and Register Descriptions
3.3.2.2.3 Data Direction Register (DDRS)
Module Base + $A
Read:
Write:
Reset:
Bit 7
DDRS7
0
6
5
4
3
2
1
DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1
0
0
0
0
0
0
Figure 3-10. Port S Data Direction Register (DDRS)
Bit 0
DDRS0
0
Read:Anytime.
Write:Anytime.
This register configures each port S pin as either input or output.
If the SPI is enabled, the SPI controls the SPI related pins (SPI_SS, SPI_SCK, SPI_MOSI, SPI_MISO)
I/O direction, and the corresponding DDRS[7:4] bits have no effect on the SPI pins I/O direction. Refer to
the SPI block description chapter for details.
When the SCI0 or SCI1 transmitters are enabled, the corresponding transmit pins, SCI0_TxD and
SCI0_TxD, I/O direction is controlled by the SCI0 and SCI1 respectively, and the corresponding DDRS3
and DDRS1 bits have no effect on their I/O direction. When the SCI0 or SCI1 receivers are enabled, the
corresponding receive pins, SCI0_RXD and SCI1_RXD, I/O direction is controlled by the SCI0 and SCI1
respectively, and the DDRS2 and DDRS0 bits have no effect on their I/O direction. Refer to the SCI block
description chapter for further details.
The DDRS[7:0] bits revert to controlling the I/O direction of the pins when the associated SPI or SCI
function is disabled.
DDRS[7:0] — Data Direction Port S
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS
or PTIS registers, when changing the DDRS register.
3.3.2.2.4 Reduced Drive Register (RDRS)
Module Base + $B
Read:
Write:
Reset:
Bit 7
RDRS7
0
6
RDRS6
0
5
RDRS5
0
4
RDRS4
0
3
RDRS3
0
2
RDRS2
0
1
RDRS1
0
Figure 3-11. Port S Reduced Drive Register (RDRS)
Bit 0
RDRS0
0
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port S output pin as either full or reduced. If the port is
used as input this bit is ignored.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
117