MC9S12NE64CPVE Datasheet, PDF (397/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

External Signal Description
15.1.2 Modes of Operation
• Normal expanded wide mode
Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus
control and status signals. This mode allows 16-bit external memory and peripheral devices to be
interfaced to the system.
• Normal expanded narrow mode
Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data.
Port E provides bus control and status signals. This mode allows 8-bit external memory and
peripheral devices to be interfaced to the system.
• Normal single-chip mode
There is no external expansion bus in this mode. The processor program is executed from internal
memory. Ports A, B, K, and most of E are available as general-purpose I/O.
• Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping, or security
related operations. The active background mode is in control of CPU execution and BDM firmware
is waiting for additional serial commands through the BKGD pin. There is no external expansion
bus after reset in this mode.
• Emulation expanded wide mode
Developers use this mode for emulation systems in which the users target application is normal
expanded wide mode.
• Emulation expanded narrow mode
Developers use this mode for emulation systems in which the users target application is normal
expanded narrow mode.
• Special test mode
Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus
control and status signals. In special test mode, the write protection of many control bits is lifted
so that they can be thoroughly tested without needing to go through reset.
• Special peripheral mode
This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is
inactive and an external (tester) bus master drives address, data, and bus control signals.
15.2 External Signal Description
In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins.
Some pins may not be bonded out in all implementations.
Table 15-1 outlines the pin names and functions and gives a brief description of their operation reset state
of these pins and associated pull-ups or pull-downs is dependent on the mode of operation and on the
integration of this block at the chip level (chip dependent).
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
397