MC9S12NE64CPVE Datasheet, PDF (132/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.6.3 Data Direction Register (DDRL)
Module Base + $2A
Read:
Write:
Reset:
Bit 7
0
—
6
5
4
DDRL6 DDRL5 DDRL4
0
0
0
= Reserved or unimplemented
3
DDRL3
0
2
DDRL2
0
1
DDRL1
0
Figure 3-41. Port L Data Direction Register (DDRL)
Bit 0
DDRL0
0
Read:Anytime.
Write:Anytime.
DDRL[6:0] — Data Direction Port L
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
This register configures each port L pin as either input or output. If EPHY port status LEDs are enabled,
pins PL[4:0] are forced to be outputs and this register has no effect on their directions. Refer to the EPHY
block description chapter for more information.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTL
or PTIL registers, when changing the DDRL register.
3.3.2.6.4 Reduced Drive Register (RDRL)
Module Base + $2B
Read:
Write:
Reset:
Bit 7
0
—
6
5
4
RDRL6 RDRL5 RDRL4
0
0
0
= Reserved or unimplemented
3
RDRL3
0
2
RDRL2
0
1
RDRL1
0
Figure 3-42. Port L Reduced Drive Register (RDRL)
Bit 0
RDRL0
0
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port L output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRL[6:0] — Reduced Drive Port L
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
MC9S12NE64 Data Sheet, Rev. 1.1
132
Freescale Semiconductor