MC9S12NE64CPVE Datasheet, PDF (47/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Signal Description
NOTE
Signals shown in bold are not available in the 80-pin package.
NOTE
If the port pins are not bonded out in the chosen package, the user must
initialize the registers to be inputs with enabled pull resistance to avoid
excess current consumption. This applies to the following pins:
(80-Pin TQFP-EP): Port A[7:0], Port B[7:0], Port E[7,6,5,3,2], Port K[7:0];
Port G[7]; Port L[6:5]
1.2.3 Detailed Signal Descriptions
1.2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the external clock and crystal driver pins. Upon reset, all the device clocks are
derived from the EXTAL input frequency. XTAL is the crystal output.
1.2.3.2 RESET — External Reset Pin
RESET is an active-low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin must not
include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing. The RESET pin includes an internal pull-up device.
1.2.3.3 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL filter. See A.12.3.1, “XFC Component Selection,” and the CRG block
description chapter for more detailed information.
1.2.3.4 BKGD / MODC / TAGHI — Background Debug / Tag High / Mode Pin
The BKGD / MODC / TAGHI pin is used as a pseudo-open-drain pin for background debug
communication. It is used as an MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. In MCU expanded modes of operation, while
instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of
the instruction word being read into the instruction queue. This pin always has an internal pull-up.
1.2.3.5 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA[7:0] are general-purpose I/O pins. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus. PA[7:0] pins are not available in the 80-pin package version.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
47