MC9S12NE64CPVE Datasheet, PDF (85/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Memory Map and Register Definition
7
6
5
4
3
2
1
0
R
FDATALO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-16. Flash Data Low Register (FDATALO)
All FDATAHI and FDATALO bits are readable but are not writable. After an array write as part of a
command write sequence, the FDATA registers will contain the data written. At the completion of a data
compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression
signature is readable in the FDATA registers until a new command write sequence is started.
2.3.2.12 RESERVED2
This register is reserved for factory testing and is not accessible.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-17. RESERVED2
All bits read 0 and are not writable.
2.3.2.13 RESERVED3
This register is reserved for factory testing and is not accessible.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-18. RESERVED3
All bits read 0 and are not writable.
2.3.2.14 RESERVED4
This register is reserved for factory testing and is not accessible.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
85