MC9S12NE64CPVE Datasheet, PDF (392/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 14 Interrupt (INTV1)
14.6.1 Interrupt Registers
The INT registers are accessible only in special modes of operation and function as described in
Section 14.3.2.1, “Interrupt Test Control Register,” and Section 14.3.2.2, “Interrupt Test Registers,”
previously.
14.6.2 Highest Priority I-Bit Maskable Interrupt
When the optional HPRIO block is implemented, the user is allowed to promote a single I-bit maskable
interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and
passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces
the promoted interrupt source.
14.6.3 Interrupt Priority Decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the
CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt
request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority
interrupt request could override the original exception that caused the CPU to request the vector. In this
case, the CPU will receive the highest priority vector and the system will process this exception instead of
the original request.
NOTE
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not be processed.
If for any reason the interrupt source is unknown (e.g., an interrupt request becomes inactive after the
interrupt has been recognized but prior to the vector request), the vector address will default to that of the
last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt
vector when there has never been a pending interrupt request, the INT will provide the software interrupt
(SWI) vector address.
14.7 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request
by the CPU is shown in Table 14-5.
Table 14-5. Exception Vector Map and Priority
Vector Address
0xFFFE–0xFFFF
0xFFFC–0xFFFD
0xFFFA–0xFFFB
0xFFF8–0xFFF9
0xFFF6–0xFFF7
0xFFF4–0xFFF5
Source
System reset
Crystal monitor reset
COP reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
XIRQ signal
MC9S12NE64 Data Sheet, Rev. 1.1
392
Freescale Semiconductor