MC9S12NE64CPVE Datasheet, PDF (54/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 1 MC9S12NE64 Device Overview
1.2.3.40 PL6 — Port L I/O Pin 6
PL6 is a general-purpose I/O pin. While in reset and immediately out of reset, the PL6 pin is configured
as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description
chapter for information about pin configurations.
1.2.3.41 PL5 — Port L I/O Pin 5
PL5 is a general-purpose I/O pin. While in reset and immediately out of reset, the PL5 pin is configured
as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description
chapter for information about pin configurations.
1.2.3.42 PL4 / COLLED — Port L I/O Pin 4
PL4 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the collision status signal (COLLED). While in reset and
immediately out of reset the PL4 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.43 PL3 / DUPLED — Port L I/O Pin 3
PL3 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the duplex status signal (DUPLED). While in reset and
immediately out of reset, the PL3 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.44 PL2 / SPDLED — Port L I/O Pin 2
PL2 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the speed status signal (SPDLED). While in reset and
immediately out of reset, the PL2 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.45 PL1 / LNKLED — Port L I/O Pin 1
PL1 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the link status signal (LNKLED). While in reset and
immediately out of reset, the PL1 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
MC9S12NE64 Data Sheet, Rev 1.0
54
Freescale Semiconductor