MC9S12NE64CPVE Datasheet, PDF (399/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Memory Map and Register Definition
Table 15-1. External System Pins Associated With MEBI (continued)
Pin Name
PE4/ECLK
Pin Functions
PE4
ECLK
PE3/LSTRB/ TAGLO PE3
LSTRB
SZ8
TAGLO
PE2/R/W
PE1/IRQ
PE0/XIRQ
PK7/ECS
PK6/XCS
PK5/X19
thru
PK0/X14
PE2
R/W
PE1
IRQ
PE0
XIRQ
PK7
ECS
PK6
XCS
PK5–PK0
X19–X14
Description
General-purpose I/O pin, see PORTE and DDRE registers.
Bus timing reference clock, can operate as a free-running clock at the system
clock rate or to produce one low-high clock per visible access, with the high
period stretched for slow accesses. ECLK is controlled by the NECLK bit in
PEAR, the IVIS bit in MODE, and the ESTR bit in EBICTL.
General-purpose I/O pin, see PORTE and DDRE registers.
Low strobe bar, 0 indicates valid data on D7–D0.
In special peripheral mode, this pin is an input indicating the size of the data
transfer (0 = 16-bit; 1 = 8-bit).
In expanded wide mode or emulation narrow modes, when instruction tagging
is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of
the instruction word being read into the instruction queue.
General-purpose I/O pin, see PORTE and DDRE registers.
Read/write, indicates the direction of internal data transfers. This is an output
except in special peripheral mode where it is an input.
General-purpose input-only pin, can be read even if IRQ enabled.
Maskable interrupt request, can be level sensitive or edge sensitive.
General-purpose input-only pin.
Non-maskable interrupt input.
General-purpose I/O pin, see PORTK and DDRK registers.
Emulation chip select
General-purpose I/O pin, see PORTK and DDRK registers.
External data chip select
General-purpose I/O pins, see PORTK and DDRK registers.
Memory expansion addresses
Detailed descriptions of these pins can be found in the device overview chapter.
15.3 Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Table 15-2. Detailed
descriptions of the registers and bits are given in the subsections that follow. On most chips the registers
are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
399