MC9S12NE64CPVE Datasheet, PDF (323/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Memory Map and Register Descriptions
11.3.2.10 MII Management PHY Address (MPADR)
Module Base + $10
7
6
5
4
3
2
1
0
R
0
0
0
W
PADDR
RESET:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-11. MII Management PHY Address (MPADR)
Read: Anytime.
Write: Anytime, but the user must not change this field while BUSY is set.
PADDR — MII Management PHY Address
This field specifies 1 of up to 32 attached PHY devices. The default address for the internal PHY after
reset is 0, but can be changed by writing the PHY address register.
11.3.2.11 MII Management Register Address (MRADR)
Module Base + $11
7
6
5
4
3
2
1
0
R
0
0
0
W
RADDR
RESET:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-12. MII Management Register Address (MRADR)
Read: Anytime.
Write: Anytime, but the user must not change this field while BUSY is set.
RADDR — MII Management Register Address
This field selects 1 of the 32 MII registers of a PHY device to be accessed. The default address for the
internal PHY after reset is 0, but can be changed by writing the PHY address register.
11.3.2.12 MII Management Write Data (MWDATA)
Module Base + $12
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
WDATA
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-13. MII Management Write Data (MWDATA)
Read: Anytime.
Write: Anytime, but the user must not change this field while BUSY is set.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
323