MC9S12NE64CPVE Datasheet, PDF (482/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 18 Debug Module (DBGV1)
PAGSEL
7
6
DBGCXX
DBGCXH[15:12]
EXTCMP
0
5
0
4
3
2
BIT 15 BIT 14 BIT 13 BIT 12
1
BIT 0
SEE NOTE 1
PORTK/XAB
XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 18-11.
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Figure 18-10. Comparator C Extended Comparison in BKP/DBG Mode
18.3.2.6 Debug Comparator C Register (DBGCC)
15
R Bit 15
14
Bit 14
13
Bit 13
12
Bit 12
11
Bit 11
10
Bit 10
9
Bit 9
8
Bit 8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-11. Debug Comparator C Register High (DBGCCH)
R
W
Reset
Field
15:0
7
Bit 7
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-12. Debug Comparator C Register Low (DBGCCL)
Table 18-12. DBGCC Field Descriptions
Description
Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare
the address bus bits [15:0] to a logic 1 or logic 0. See Table 18-13.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
MC9S12NE64 Data Sheet, Rev. 1.1
482
Freescale Semiconductor