MC9S12NE64CPVE Datasheet, PDF (45/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Signal Description
Table 1-4. Signal Properties (Sheet 3 of 4)
orig. order
80 Pin
No.
112 Pin
No.
Pin
Name
Function
1
Pin
Name
Function
2
Pin
Name
Function
3
Power
Domain
Internal Pull
Resistor
CTRL
Reset
State
Description
Reset
State
4
32
44
RESET
—
—
VDDX None None External reset pin Input
66
33
45
VDDPLL
—
—
See Table 1-5
3
34
46
XFC
—
—
VDDPLL NA
NA PLL filter pin
67
35
47
VSSPLL
—
—
See Table 1-5
1
36
48
EXTAL
—
2
37
49
XTAL
—
—
VDDPLL NA
—
VDDPLL NA
NA
Oscillator pins
NA
Input
Output
68
38
50
TEST
—
—
VDDX None None Must be grounded Input
41
—
51
PL6
—
—
VDDX
PERL/
PPSL
Disabled Port L I/O pin
Input
42
—
52
PL5
—
—
VDDX
PERL/
PPSL
Disabled Port L I/O pin
Input
Port E I/O pin; low
10
—
53
PE3
TAGLO
LSTRB VDDX PUCR Up strobe; tag signal Input
low
Port E I/O pin; R/W
11
—
54
PE2
R/W
—
VDDX PUCR Up in expanded
Input
modes
12
39
55
PE1
IRQ
—
VDDX PUCR
Up
Port E input; external
interrupt pin
Input
13
40
56
PE0
XIRQ
Port E input;
—
VDDX PUCR Up non-maskable
interrupt pin
Input
Background debug;
5
41
57
BKGD
MODC
TAGHI VDDX None
Up mode pin; tag signal Input
high
43
42
58
PL4
COLLED
—
VDDX
PERL/
PPSL
Disabled
Port L I/O pin; EPHY
collision LED
Input
44
43
59
PL3
DUPLED
—
VDDX
PERL/
PPSL
Disabled
Port L I/O pin; EPHY
full duplex LED
Input
14
—
60–63
77–80
PA[7:0]
ADDR[15:8]/
DATA[15:8]
—
VDDX
Port A I/O pin;
PUCR Disabled multiplexed
address/data
Input
69
44
64
VSS2
—
—
See Table 1-5
70
45
65
VDD2
—
—
See Table 1-5
61
46
66 PHY_RBIAS
—
Bias control:1.0%
—
PHY_
VSSA
NA
NA
external resistor
Analog
(see the Electricals Input
Chapter for R_Bias)
71
47
67 PHY_VSSA
—
—
See Table 1-5
72
48
68 PHY_VDDA
—
—
See Table 1-5
73
49
69 PHY_VDDTX
—
—
See Table 1-5
58
50
70
PHY_TXP
—
—
PHY_
VDDTX
NA
NA
Twisted pair output +
Analog
Output
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
45