MC9S12NE64CPVE Datasheet, PDF (345/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Functional Description
MII_COL, MII_CRS, MII_MDC, and MII_MDIO signals are disabled. During loopback, the MII to
external and internal PHYs are disabled. Loopback mode requires that the user set the FDX bit to configure
for full-duplex mode. Loopback connects the outs to the ins and relies on the unidirectional nature of full
duplex to transfer data in parallel. The bidirectional nature of half duplex does not allow the RX to accept
transmit data without using some kind of intermediate storage buffer.
11.4.8 Software Reset
The EMAC provides a software reset capability. When the MACRST bit is set, all registers are reset to
their default values. The EMACE bit is cleared. The receiver and transmitter are initialized. Any reception
and/or transmission currently in progress is abruptly aborted.
11.4.9 Interrupts
When an interrupt event occurs, a bit is set in the IEVENT register. Note that bits in the IEVENT register
are set by the event and remain set until cleared by software. If a bit in the IEVENT register is set and the
corresponding bit is set in the IMASK register, the corresponding interrupt signal asserts. Individual
interrupts are cleared by software by writing a 1 to the corresponding bit in the IEVENT register.
The interrupt sources are listed in Table 11-12.
Table 11-12. Interrupt Vectors
Interrupt Source
Receive Flow Control (RFCIF)
Babbling Receive Error (BREIF)
Receive Error (RXEIF)
Receive Buffer A Overrun (RXAOIF)
Receive Buffer B Overrun (RXBOIF)
Receive Buffer A Complete (RXACIF)
Receive Buffer B Complete (RXBCIF)
MII Management Transfer Complete (MMCIF)
Late Collision (LCIF)
Excessive Collision (ECIF)
Frame Transmission Complete (TXCIF)
CCR Mask
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Local Enable
IMASK (RFCIE)
IMASK (BREIE)
IMASK (RXEIE)
IMASK (RXAOIE)
IMASK (RXBOIE)
IMASK (RXACIE)
IMASK (RXBCIE)
IMASK (MMCIE)
IMASK (LCIE)
IMASK (ECIE)
IMASK (TXCIE)
11.4.10 Debug and Stop
During system debug (freeze) mode, the EMAC functions normally.When the system enters low-power
stop mode, the EMAC is immediately disabled. Any receive in progress is dropped and any PAUSE
timeout is cleared. The user must not enter low-power stop mode while TXACT or BUSY is set.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
345