MC9S12NE64CPVE Datasheet, PDF (414/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.13 Reserved Register
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-17. Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to
this register have no effect.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
15.3.2.14 IRQ Control Register (IRQCR)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
IRQE
IRQEN
W
Reset
0
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-18. IRQ Control Register (IRQCR)
Read: See individual bit descriptions below
Write: See individual bit descriptions below
Table 15-12. IRQCR Field Descriptions
Field
7
IRQE
6
IRQEN
Description
IRQ Select Edge Sensitive Only
Special modes: read or write anytime
Normal and Emulation modes: read anytime, write once
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
External IRQ Enable
Normal, emulation, and special modes: read or write anytime
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
Note: When IRQEN = 0, the edge detect latch is disabled.
MC9S12NE64 Data Sheet, Rev. 1.1
414
Freescale Semiconductor