MC9S12NE64CPVE Datasheet, PDF (226/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64 Device Overview

Chapter 7 Analog-to-Digital Converter (ATD10B8CV3)
7.4 Functional Description
The ATD is structured in an analog and a digital sub-block.
7.4.1 Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V_DDA and V_SSA allow to isolate noise of other MCU circuitry from the analog sub-block.
7.4.1.1 Sample and Hold Machine
The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them
as capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw
their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the
analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V_SSA to V_DDA.
7.4.1.2 Analog Input Multiplexer
The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold
machine.
7.4.1.3 Sample Buffer Amplifier
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly
charged to the sample potential.
7.4.1.4 Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8
or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the
stored analog sample potential with a series of digitally generated analog potentials. By following a binary
search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled
potential.
When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent
current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power
consumption.
Only analog input signals within the potential range of V_RL to V_RH (A/D reference potentials) will result
in a non-railed digital output codes.
MC9S12NE64 Data Sheet, Rev. 1.1
226
Freescale Semiconductor