W90P710CD Datasheet, PDF (92/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
RESERVED
WRBEN DCAEN ICAEN
BITS
[31:3]
[2]
[1]
[0]
RESERVED
WRBEN
DCAEN
ICAEN
DESCRIPTION
-
Write buffer enable
Write buffer is disabled after reset.
1 = Enable write buffer
0 = Disable write buffer
D-Cache enable
D-Cache is disabled after reset.
1 = Enable D-cache
0 = Disable D-cache
I-Cache enable
I-Cache is disabled after reset.
1 = Enable I-cache
0 = Disable I-cache
Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y Flush I-Cache and D-Cache
y Load and lock I-Cache and D-Cache
y Unlock I-Cache and D-Cache
y Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
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