W90P710CD Datasheet, PDF (302/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
BITS
[31:30]
[29:20]
Reserved
VSPW
[19:10] VBPD
[9:0]
VFPD
DESCRIPTIONS
Reserved
Vertical sync pulse width determines the VSYNC pulse's high level
width by counting the number of inactive lines.
Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period.
Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period.
LCD Timing Control 4 Register (LCDTCON4)
REGISTER
ADDRESS R/W
DESCRIPTION
LCDTCON4 0xFFF0_80BC R/W LCD Timing Control 4
RESET VALUE
0x0000_0000
31
30
29
28
27
Reserved
23
22
21
20
19
PCD[6:0]
15
14
13
12
11
Reserved
7
6
5
4
3
LCDPRESC
26
25
24
PCD[9:7]
18
17
16
Reserved
10
9
8
PLLRDY
2
1
0
CLKSEL
BITS
[31:27]
Reserved
[26:17] PCD
[16:9]
[8]
Reserved
PLLRDY
[7:1]
LCDPRESC
[0]
CLKSEL
DESCRIPTIONS
Reserved
The ten-bit PCD field is used to derive the LCD panel clock
frequency VCLK from LCD controller clock:
VCLK=LCDCLK/(PCD+2)
Reserved
Indicate LCDC that PLL is ready, can switch pixel clock source to
PLL clock
These bits pre-scale counter the LCD controller clock
Scale_CLK = PLL_FIN / ( 2*( LCDPRESC + 1 ) )
This bit driver the LCD controller clock source.
0 = external PLL clock 1 = AHB Bus clock
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