W90P710CD Datasheet, PDF (483/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
mw_ss_o
mw_sclk_o
mw_so_o
mw_si_i
LSB
(Tx[0])
Tx[1]
Tx[2]
Tx[3]
Tx[4]
Tx[5]
Tx[6]
MSB
(Tx[7])
LSB
(Rx[0])
Rx[1]
Rx[2]
Rx[3]
Rx[4]
Rx[5]
Rx[6]
MSB
(Rx[7])
CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,
CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0
Fig. 6.19.1.2 Alternate Phase SCLK Clock Timing
6.19.2 USI Registers Map
R: read only, W: write only, R/W: both read and write
REGISTER ADDRESS R/W
DESCRIPTION
USI_CNTRL 0xFFF8_6200 R/W Control and Status Register
USI_DIVIDER 0xFFF8_6204 R/W Clock Divider Register
USI_SSR
0xFFF8_6208 R/W Slave Select Register
Reserved
0xFFF8_620C N/A Reserved
USI_Rx0
0xFFF8_6210 R Data Receive Register 0
USI_Rx1
0xFFF8_6214 R Data Receive Register 1
USI_Rx2
0xFFF8_6218 R Data Receive Register 2
USI_Rx3
0xFFF8_621C R Data Receive Register 3
USI_Tx0
0xFFF8_6210 W Data Transmit Register 0
USI_Tx1
0xFFF8_6214 W Data Transmit Register 1
USI_Tx2
0xFFF8_6218 W Data Transmit Register 2
USI_Tx3
0xFFF8_621C W Data Transmit Register 3
NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last.
RESET VALUE
0x0000_0004
0x0000_0000
0x0000_0000
N/A
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
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