W90P710CD Datasheet, PDF (353/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
BITS
[31:5]
[4]
[3]
[2]
[1]
[0]
Reserved
nDBGACK_EN
MSIE
RLSIE
THREIE
RDAIE
DESCRIPTIONS
-
ICE debug mode acknowledge enable
0 = When DBGACK is high, the UART receiver time-out clock will be
held
1 = No matter what DBGACK is high or not, the UART receiver timer-
out clock will not be held
MODEM Status Interrupt (Irpt_MOS) Enable
0 = Mask off Irpt_MOS
1 = Enable Irpt_MOS
Receive Line Status Interrupt (Irpt_RLS) Enable
0 = Mask off Irpt_RLS
1 = Enable Irpt_RLS
Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable
0 = Mask off Irpt_THRE
1 = Enable Irpt_THRE
Receive Data Available Interrupt (Irpt_RDA) Enable and
Time-out Interrupt (Irpt_TOUT) Enable
0 = Mask off Irpt_RDA and Irpt_TOUT
1 = Enable Irpt_RDA and Irpt_TOUT
HSUART Divider Latch (Low Byte) Register (HSUART_DLL)
REGISTER OFFSET R/W
HSUART_DLL 0x00 R/W
DESCRIPTION
Divisor Latch Register (LS) (DLAB = 1)
RESET VALUE
0x0000_0000
31
30
23
22
15
14
7
6
29
28
27
26
Reserved
21
20
19
18
Reserved
13
12
11
10
Reserved
5
4
3
2
Baud Rate Divider (Low Byte)
25
24
17
16
9
8
1
0
Publication Release Date: September 19, 2006
- 353 -
Revision B2