W90P710CD Datasheet, PDF (356/552 Pages) Winbond – 32-BIT ARM7TDMI-BASED MCU

W90P710CD/W90P710CDG
Interrupt Control Functions
IIR [3:0] PRIORITY INTERRUPT TYPE
---1
--
None
0110
Highest
Receiver Line Status
(Irpt_RLS)
0100
Second
Received Data
Available (Irpt_RDA)
1100
Second
Receiver FIFO Time-
out (Irpt_TOUT)
0010
Third
Transmitter Holing
Register Empty
(Irpt_THRE)
INTERRUPT SOURCE
None
Overrun error, parity
error, framing error, or
break interrupt
Receiver FIFO threshold
level is reached
Receiver FIFO is non-
empty and no activities
are occurred in the
receiver FIFO during the
TOR defined time
duration
Transmitter holding
register empty
INTERRUPT RESET
CONTROL
--
Reading the LSR
Receiver FIFO drops
below the threshold
level
Reading the RBR
Reading the IIR (if
source of interrupt is
Irpt_THRE) or
writing into the THR
0000
Fourth
MODEM Status
(Irpt_MOS)
The CTS bits are changing ^{Reading the MSR}
state .
(optional)
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550.
HSUART FIFO Control Register (HSUART_FCR)
REGISTER OFFSET R/W
HSUART_FCR 0x08
W
DESCRIPTION
FIFO Control Register
RESET VALUE
Undefined
31
30
29
23
22
21
15
14
13
7
6
5
RFITL
28
27
26
Reserved
20
19
18
Reserved
12
11
10
Reserved
4
3
2
DMS
TFR
25
17
9
1
RFR
24
16
8
0
FME
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